1. Field of the Invention
The invention relates to a method for integrating a high-voltage (HV) device and a low-voltage (LV) device, and more particularly to an HV device process compatible with an LV process for an HV device with a narrowed width design, which increases punch through voltage and bulk-drain voltage (VBD) thereof.
2. Description of the Related Art
In the current semiconductor manufacturing process, controllers, memories, low-voltage (LV) circuits and power high-voltage (HV) devices are largely integrated into a single chip to achieve a single-chip system. The power device, such as VDMOS, IGBT and LDMOS, is employed to increase power switching efficiency and decrease the loss of energy resources. Since HV and LV devices with different breakdown voltages are required on a single chip, achieving compatibility in the HV and LV device process has become an important issue.
In the conventional HV device process, a polysilicon gate formed on a silicon substrate is used as a mask and then a self-aligned source/drain region with a double diffused drain (DDD) structure is formed in the silicon substrate. Commonly, in order to suppress the hot electron effect and to increase the breakdown voltage in the source/drain region, a lightly doped region is formed in the silicon substrate under the source/drain region, and then a high-temperature drive-in process is performed to form the DDD structure. However, in the procedure integrating HV and LV devices, the structure and thermal budget for the HV device are different from those for the LV device. The grade region, the drive-in process on the lightly doped region for the DDD structure may vary in the diffusing regions of the LV device, resulting in unstable electrical properties in the LV device.
U.S. Pat. No. 6,509,243 discloses a method for integrating HV and LV devices, which is now described with reference to FIGS. 1A˜1E. In FIG. 1A, a semiconductor silicon substrate 10 comprises an HV device region 12H and an LV device region 12L. First, a nitride insulating layer 16 is deposited on the substrate 10, and the nitride insulating layer 16 is then patterned to expose a portion of the substrate 10 used as a predetermined isolation region. An oxidation process is then performed on the exposed portion of the substrate 10 to form a field oxide isolation region 14 which isolates the HV device region 12H from the LV device region 12L.
Next, in FIG. 1B, a photoresist layer 18 is formed on the substrate 10 to expose a portion of the nitride insulating layer 16 in the HV device region 12H, in which the substrate 10 under the exposed portion corresponds to a predetermined source/drain region of the HV device region 12H. Then, using ion implantation with the photoresist layer 18 as a mask, a doped region 20 is formed in the substrate 10 under the exposed portion of the nitride insulating layer 16. Next, in FIG. 1C, after sequentially removing the photoresist layer 18 and the nitride insulating layer 16, a high-temperature drive-in process is performed to forwardly diffuse the doped ions in the doped region 20 into the substrate 10 and laterally diffuse into a portion under the field isolation region 14, thus the doped region 20 is transformed into a grade diffusion region 20a. 
Next, in FIG. 1D, an HV gate structure 26H and an LV gate structure 26L are formed on the substrate 10 in the HV device region 12H and the LV device region 12L, respectively. Each HV gate structure 26H and the LV gate structure 26L comprises a gate oxide layer 22 and a polysilicon gate layer 24, and the grade diffusion region 20a in the substrate 10 is at the periphery of the HV gate structure 26H.
Next, in FIG. 1E, after covering the HV device region 12H with a photoresist material, light implantation performed employing with the LV gate structure 26L as a mask, a lightly doped region 28 is formed in the substrate 10 within the LV device region 12L. After removing the photoresist material from the HV device region 12H, an insulating spacer 30 is formed on the sidewalls of the HV gate structure 26H and the LV gate structure 26L. Then, heavy implantation is performed employing the HV gate structure 26H, the LV gate structure 26L and the insulating spacer 30 as a mask, a heavily doped region 32H is formed in the grade diffusion region 20a within the HV device region 12H, and a heavily doped region 32L is formed in the lightly doped region 28 within the LV device region 12L. Therefore, in the HV device region 12H, the combination of the grade diffusion region 20a and the lightly doped region 32H serves as a double diffused drain (DDD) structure. In the LV device region, the heavily doped region 32L serves as a source/drain region, and the lightly doped region 28 serves as a lightly doped drain (LDD) structure.
In a narrowed width design for an HV device, however, it is difficult to control the bulk-drain voltage (VBD) of the HV device because t heavy implantation is performed in the HV device region 12H and the LV device region 12L simultaneously. Also, as the channel length decreases, the electron punch through issue becomes problematic. Accordingly, an HV device process which can increase the active distance between the source region and the drain region of the HV device is called for.